Data transfer devices for transferring data across an asynchronous boundary have been used in the past. In general, these data transfer devices allow a packet of data to be transferred from a first time domain across an asynchronous boundary to a second time domain.
FIG. 1A shows a conventional data transfer device, shown generally by reference numeral 1, for transferring packets of data across an asynchronous boundary 6 from a first time domain to a second time domain. As can be seen from FIG. 1A, two receivers/transmitters, shown generally by reference numerals 2 and 4, are used to transfer data across the asynchronous boundary 6. Each receiver/transmitter 2, 4 can send packets of data across the asynchronous boundary 6 in only one direction. In the device 1 shown in FIG. 1A, the first receiver/transmitter 2 transmits packets of data from the second time domain on Side B of the asynchronous boundary 6 to the first time domain on Side A of the asynchronous boundary 6. The second receiver/transmitter 4 transmits packets of data in the opposite direction from Side A to Side B. Each receiver/transmitter 2, 4 operates independently of the other and has separate request and acknowledge signals, shown in FIG. 1A by the symbols REQ.sub.BA, ACK.sub.BA, REQ.sub.AB, ACK.sub.AB.
FIG. 1B is a logic table 20 showing the transitions of signals on Side A and Side B during a data transfer from Side A to Side B. As shown in steps 1 to 3 of FIG. 1B, when packet of data A is to be sent from Side A to Side B, the packet of data A is stored in memory unit 8A of the second receiver/transmitter 4 and a request signal REQ.sub.AB is sent across the asynchronous boundary 6 from flip flop 9A to synchronizer 12B on Side B. It generally takes two clock cycles on the receiver clock, in this case the clock CLK.sub.B in Time Domain B, to receive the request signal REQ.sub.AB from flip flop 9A. Once Side B receives the request signal REQ.sub.AB from Side A, Side B uses or latches the packet of data A stored in memory unit 8A.
Once Side B receives packet of data A, Side B asserts an acknowledge signal ACK.sub.BA through flip flop 11B which is sent across the asynchronous boundary 6 to synchronizer 10A, as shown in steps 4 to 6 of FIG. 1B. It generally takes two clock cycles of the transmitter clock, in this case the clock CLK.sub.A in the first time domain, to receive the acknowledge signal ACK.sub.BA. The request signal REQ.sub.AB and the acknowledge signal ACK.sub.BA are then de-asserted as shown in steps 7 to 10 of FIG. 1B. A second packet of data B can then be stored in memory unit 8A of receiver/transmitter 4, as shown in step 11 of FIG. 1B, to be sent to Side B. If data is to be sent from Side B to Side A, receiver/transmitter combination 2 is used in a similar manner.
It is apparent that the receiver/transmitter combinations 2, 4 each send two handshake signals, namely the REQ.sub.BA and REQ.sub.AB signals and the ACK.sub.AB and ACK.sub.BA signals, respectively, to transfer each packet of data across the asynchronous boundary 6. This decreases the efficiency of the prior art systems because at least four clock cycles, two cycles of clock CLK.sub.A in the first time domain and two cycles of clock CLK.sub.B in the second time domain, are required to send each packet of data.
Another disadvantage of the prior art system is that there are a large number of gateways required to send and receive the request signals REQ.sub.AB, REQ.sub.BA and the acknowledge signals ACK.sub.AB, ACK.sub.BA. As shown from FIG. 1A, there is a total of twelve flip flops required to effect the flow of data between Side A and Side B. The number of flip flops increases the cost of the device and decreases the available area or real estate on the chip or board upon which the device is installed.
Also, the prior art system is less reliable and prone to metastability failures because of the number of handshake signals REQ.sub.AB, REQ.sub.BA, ACK.sub.AB and ACK.sub.BA required and the number of gateways required to send and receive these handshake signals. A metastability failure results when data or a signal, such as the request signals REQ.sub.AB, REQ.sub.BA, or the acknowledge signals ACK.sub.AB, ACK.sub.BA, is received at the same time as the receiving clock signal, either CLK.sub.A or CLK.sub.B, is changing.
If this happens, the output from the gateway receiving the data or signal is unstable. The amount of time that the gateway is unstable is a decaying function which is a physical characteristic of the flip flop gateway. This decreases the efficiency of the device, and, if the gateway stays unstable until the next cycle of receiving data, circuit failure could result. Therefore, there is a possibility of a metastability failure in the prior art devices each time one of the four handshake signals REQ.sub.AB, REQ.sub.BA, ACK.sub.AB or ACK.sub.BA is received.